The invention relates to a DRAM cell configuration and a method for fabricating it.
In known dynamic random access memory (DRAM) cell configurations, memory cells having one transistor, so-called one-transistor memory cells, are usually used. Such a one-transistor memory cell contains a storage capacitor in addition to the transistor, which forms a read-out transistor. An information item is stored in the storage capacitor in the form of an electric charge that represents a logic value, 0 or 1. By driving the read-out transistor via a word line, the information item can be read out via a bit line.
Since the storage density increases from memory generation to memory generation, the required area of the memory cell must be reduced from generation to generation. Since limits are imposed on the reduction of the size of the memory cell due to the minimum feature size that can be fabricated in the respective technology, this is also associated with an alteration of the construction of the memory cells. Thus, up to the 1 Mbit generation of DRAM cell configurations, both the read-out transistor and the storage capacitor were realized as planar components. Starting from the 4 Mbit memory generation, a three-dimensional configuration of the storage capacitor and the read-out transistor had to be effected.
In this case, the storage capacitors are realized, in particular, not in planar fashion but rather in trenches. Such memory cells are known as deep trench memory cells.
Such a storage capacitor contains two electrodes that are isolated by a dielectric and are disposed lying one above the other in a trench in a manner jointly surrounded by an insulator layer. The trenches are incorporated into a semiconductor substrate and open out at the topside thereof. The top electrode is preferably composed of doped polysilicon. The insulator layer of a trench has, at the topside thereof, an opening through which dopants are outdiffused in the polysilicon. The zone of the outdiffusion behind the opening of the insulator layer forms a buried strap contact for connecting the storage capacitor to the read-out transistor. The read-out transistor has a gate electrode and a source/drain region. The gate electrode is applied at a predetermined distance from the storage capacitor at the topside of the semiconductor substrate. Implantation of dopants produces the source/drain region, which lies above the buried strap contact at the topside of the semiconductor substrate and adjoins the buried strap contact. The boundary regions of the buried strap contact and of the adjoining source/drain region, which boundary regions adjoin the interior of the semiconductor substrate, form a p/n junction of the memory cell.
U.S. Pat. No. 5,555,520 describes a trench capacitor for DRAM cells which has a monocrystalline electrode and which is connected to the gate electrode of the transistor via a buried strap.
The reference titled xe2x80x9cSubstrate Plate Trench DRAM Cell with an Increased Background Doping (Halo) Surrounding the Strap Regionxe2x80x9d, IBM Technical Disclosure Bulletin, Vol. 37 No. 10 October 1994, pages 341-342, describes a method which produces a highly concentrated region (halo) surrounding a buried strap contact, the xe2x80x9chaloxe2x80x9d having the opposite conductivity to the buried strap and the connected source/drain region.
An essential problem in DRAM cell configurations is that the information stored in a memory cell is lost through leakage currents in the memory cell. The time within which the information in a memory cell is lost is called the retention time. Therefore, the information items stored in the memory cells of a DRAM cell configuration must be refreshed at regular time intervals. The time intervals within which the refreshes are affected are called refresh times.
As storage capacities of DRAM cell configurations increase, it becomes more and more difficult to achieve the required retention times. Therefore, optimization of the leakage current paths present is gaining more and more importance.
In this case, the essential leakage current path is formed by the p/n junction at the boundary regions of the buried strap contact and of the source/drain region. Such leakage currents are caused, in particular, by generation centers such as, for example, point defects that arise during the outdiffusion of dopants from the polysilicon layer forming the electrode of the storage capacitor. Moreover, two-dimensional crystal defects such as dislocations, for example, may adhere at the interface between the buried strap contact and the semiconductor substrate, which is preferably formed by a silicon single crystal, or arise there as a result of epitaxial recrystallization of polysilicon. If such defects lie in or at a short distance from the space charge zone of the p/n junction, then this can lead to a considerable increase in the leakage current of the p/n junction.
It is accordingly an object of the invention to provide a DRAM cell configuration and a method for fabricating the DRAM cell which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the retention times in DRAM cell configuration is increased.
With the foregoing and other objects in view there is provided, in accordance with the invention, a dynamic random access memory (DRAM) cell configuration. The DRAM cell configuration contains a semiconductor substrate having trenches formed therein, an insulating layer having an opening formed therein, and storage capacitors disposed in the trenches of the semiconductor substrate. Each of the storage capacitors has an electrode being isolated from the semiconductor substrate by the insulating layer. Read-out transistors are provided. Each of the read-out transistors is assigned to an associated one of the storage capacitors. Each of the read-out transistors has a gate electrode and a source/drain region produced by implantation of dopants and is disposed in the semiconductor substrate. The source/drain region is connected to the electrode of an associated one of the storage capacitors through the opening in the insulating layer. Buried strap contacts are provided and each of the buried strap contacts is associated with a respective storage capacitor and connected to the source/drain region of a respective read-out transistor by an outdiffusion of further dopants from the electrode of the respective storage capacitor. The doping type of the outdiffusion and of the implantation are identical. The implantation of the source/drain region in each case extends at least as deeply into the semiconductor substrate as the outdiffusion of the buried strap contacts so that the implantation of the source/drain region forms a boundary of a space charge zone of a p/n junction.
In the cell configuration according to the invention, in the individual memory cells, the buried strap contacts are in each case superposed by the implantation of the source/drain regions, so that the implantation of the source/drain regions in each case forms the boundary of the space charge zone of the p/n junction. In this case, preferably the entire or virtually the entire area of a buried strap contact is superposed by the implantation of the source/drain region.
In order to fabricate the configuration, after the application of the gate electrodes to the semiconductor substrate, dopants are implanted selectively into the interspaces between the storage capacitors and the gate electrodes for the purpose of producing the source/drain regions. Suitable masks are used for this, the gate electrodes preferably also being at least partly masked by the masks.
By the selective implantation carried out in this way, the source/drain regions of the read-out transistors can be shifted into greater depths of the semiconductor substrate, so that the buried strap contacts are at least partly superposed by the implantation of the source/drain regions. Consequently, the boundaries of the space charge zones of the p/n junctions are no longer determined by the zones of the outdiffusion of the buried strap contacts, but rather by the regions of the implantations of the source/drain regions. What is thereby achieved is that the generation centers and defects in a buried strap contact are more than one diffusion length for minority charge carriers removed from the space charge zone of a p/n junction.
Consequently, such minority charge carriers recombine before they can reach the p/n junction and are therefore electrically inactive. This results in a considerable reduction of the leakage currents via the p/n junction and thus an increase in the retention time.
A further aspect of the method according to the invention is that the implantation of the source/drain regions is effected in large depths of the semiconductor substrate in such a way that the function of the remaining components of a memory cell, in particular the function of the read-out transistor, is not impaired.
In particular, lateral scattering of the implantation in the semiconductor substrate is largely avoided by virtue of the selective implantation of the dopants in the interspace between gate electrode and storage capacitor. Such lateral scattering would in particular, impair the blocking properties of the read-out transistor.
In accordance with an added feature of the invention, the semiconductor substrate is formed by a silicon single crystal.
In accordance with another feature of the invention, the implantation of the source/drain region is formed by phosphorous or arsenic.
In accordance with an additional feature of the invention, the electrode is formed by doped polysilicon, in particular, the doped polysilicon is arsenic-doped.
In accordance with a further feature of the invention, the insulator layer is one of a plurality of insulator layers, and the storage capacitors disposed in the trenches are electrically insulated from the surroundings by the insulator layers.
In accordance with another added feature of the invention, the insulator layers are composed of oxides fabricated by a tetraethyl orthosilicate (TEOS) method.
In accordance with another additional feature of the invention, the opening is one of a plurality of openings formed in a region of a surface of each of the trenches for each of the storage capacitors. The openings each have a diameter of about 50 nm.
In accordance with another further feature of the invention, each of the buried strap contacts is located behind one of the openings and has a width and a depth of about 100 nm in each case. An entire area of a respective buried strap contact is substantially superposed by the implantation of the source/drain region. A penetration depth of the implantation of the source/drain region is 150-200 nm.
In accordance with an added feature of the invention, the source/drain region has a width substantially corresponding to twice to three times a value of a width of the respective buried strap contact.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a dynamic random access memory (DRAM) cell configuration. The method includes the steps of providing a semiconductor substrate, fabricating trenches in the semiconductor substrate, fabricating insulator layers with openings and electrodes of storage capacitors in the trenches, outdiffusing of dopants from the electrodes through the openings for producing buried strap contacts for connection to read-out transistors associated with the storage capacitors, and forming gate electrodes of the read-out transistors on the semiconductor substrate. Source/drain regions of the read-out transistors are produced by selective implantation of further dopants into interspaces between the storage capacitors and the gate electrodes at least as deeply into the semiconductor substrate as outdiffusions formed by the buried strap contacts. The doping type of the outdiffusions of the buried strap contacts and of the implantations are identical.
In a first configuration of the method according to the invention, the implantation of the source/drain regions is effected in a single-stage process, the implantation being effected with energies up to 60 keV.
In a second configuration of the method according to the invention, the implantation of the source/drain regions is effected in a two-stage process.
The first stage of the implantation is affected after the application of the gate electrodes at relatively low energies in a region of about 15 keV. The second stage of the implantation is affected after nitride spacers have been applied to the gate electrodes. The nitride spacers mask the gate electrodes also at the lateral side walls, so that during the subsequent implantation, lateral scattering of implanted dopants below the gate electrode is made more difficult. As a result, the second stage of the implantation can be effected at higher energies, without having to fear impairment of the blocking properties of the read-out transistors through lateral scattering of the dopants. The second stage of the implantation is typically carried out with energies in the range of 20-25 keV.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a DRAM cell configuration and a method for fabricating the DRAM cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.